Modern circuit fabrication typically includes processes of forming electrical interconnection structures for interconnecting semiconductor devices in a functioning circuit. An interconnection structure may include one or more metallization levels or tiers, which are formed above the substrate and the semiconductor devices. A metallization level includes conductive paths or lines arranged in a dielectric material layer. The dielectric material layer of a metallization level may isolate the conductive paths of the metallization level from a higher and/or a lower metallization level. Conductive paths of different metallization levels may be interconnected by conductive vias extending through the dielectric layers.
A metallization level may be formed by forming patterns including trenches and holes in a dielectric layer, and filling the trenches and holes with a conductive material. Such a process may be referred to as a dual damascene process. The process may be repeated to form a stack of metallization levels on top of each other.
Patterns may be formed in a mask layer arranged above the dielectric layer using lithographic techniques and etching. Multiple patterning techniques, such as (litho-etch)x, or pitch splitting techniques, such as self-aligned double patterning (SADP) or quadruple patterning (SAQP), may be used to enable patterns with sub-lithographic critical dimensions. Multiple patterning may be combined with block techniques to enable forming of interrupted or discontinuous lines.